- CPU timing
- временная диаграмма процессора (ЦП)см. тж. timing
Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.
Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.
CPU design — is the design engineering task of creating a central processing unit (CPU), a component of computer hardware. It is a subfield of electronics engineering and computer engineering. Contents 1 Overview 2 Goals 3 Performance analysis and… … Wikipedia
CPU cache — Cache memory redirects here. For the general use, see cache. A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the… … Wikipedia
CPU multiplier — In computing, the clock multiplier (or CPU multiplier or bus/core ratio) measures the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL based… … Wikipedia
Timing attack — In cryptography, a timing attack is a side channel attack in which the attacker attempts to compromise a cryptosystem by analyzing the time taken to execute cryptographic algorithms. The attack exploits the fact that every operation in a computer … Wikipedia
Timing Definition Language — Die Timing Definition Language (TDL) erlaubt die Beschreibung des Zeitverhaltens einer komponentenbasierten Echtzeitanwendung basierend auf dem Konzept der logischen Ausführungszeit (Logical Execution Time, LET). Die LET abstrahiert von der… … Deutsch Wikipedia
CPU-Z — CPUID Développeur Franck Delattre … Wikipédia en Français
Dynamic timing verification — refers to verifying that an ASIC design is fast enough to run without errors at targeted clock rate. This is accomplished by simulating the design files used to synthesize the Integrated Circuit design. This is in contrast to static timing… … Wikipedia
List of CPU architectures — The following is a list of notable CPU architectures. Contents 1 Introduction/Overview 2 Embedded CPU architectures 3 Microcomputer CPU architectures 4 Worksta … Wikipedia
Time Stamp Counter — The Time Stamp Counter is a 64 bit register present on all x86 processors since the Pentium. It counts the number of ticks since reset, and is only accessible through the RDTSC instruction. This instruction returns the TSC in EDX:EAX. Its opcode… … Wikipedia
Universal asynchronous receiver/transmitter — A universal asynchronous receiver/transmitter (usually abbreviated UART and pronEng|ˈjuːɑrt) is a type of asynchronous receiver/transmitter , a piece of computer hardware that translates data between parallel and serial forms. UARTs are commonly… … Wikipedia
Socket A — CPU socket name = Socket 462 / A formfactors = Ceramic Pin Grid Array (CPGA) Organic Pin Grid Array (OPGA) type = PGA ZIF contacts = 453 protocol = EV6 fsb = 100 MHz, 133 MHz, 166 MHz and 200 MHz equivalent to FSB200, FSB266, FSB333 and FSB400… … Wikipedia